Method and Apparatus for Manufacturing Semiconductor Device

ABSTRACT

According to one embodiment, in a method for manufacturing a semiconductor device, a surface region of a semiconductor substrate is modified into an amorphous layer. A microwave is irradiated to the semiconductor substrate in which the amorphous layer is formed in a dopant-containing gas atmosphere so as to form a diffusion layer in the semiconductor substrate. The dopant is diffused into the amorphous layer and is activated.

CROSS REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority fromthe prior Japanese Patent Application No. 2009-161229, filed on Jul. 7,2009, the entire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to a method and anapparatus for manufacturing a semiconductor device.

BACKGROUND

In an LSI (Large Scale Integration) of a next generation or later, anextension diffusion layer with a depth shallower than 10 nm is required,and a new impurity doping technology and an ultra short time annealtechnology are being developed at present so as to form such anextremely shallow diffusion layer.

Usually, in order to form a diffusion layer, after an impurity is dopedin a semiconductor substrate, the semiconductor substrate is annealed.So as to form an extremely shallow diffusion layer using such a method,with respect to a doping technology a plasma doping and so on arenoticed considering a three dimensional structure, and with respect toan anneal technology an ultra short time anneal such as a laser anneal,a flashlight anneal and so on are noticed.

But in such technologies, a process to dope an impurity and a process toanneal are performed by separate apparatuses for manufacturing asemiconductor device, which invites an increase in equipment investmentcost. In addition, in the laser anneal and the flashlight anneal, as asurface of a semiconductor substrate is heated to a high temperature, atemperature difference is generated between the front surface and a rearsurface of the semiconductor substrate, and the semiconductor substratecurves by heat stress, so that there is a possibility to generate aproblem and so on that crystal defects such as crystal dislocation andso on generates in the semiconductor substrate.

In addition, with respect to another method to form a diffusion layer,there is a method where after an impurity layer is formed in asemiconductor substrate by an ion implantation and so on, a microwave isirradiated to the semiconductor substrate to anneal whole thesemiconductor substrate. Such a method for manufacturing a semiconductordevice is disclosed in Japanese Patent Application Publication No.10-189473.

But in such a method for manufacturing a semiconductor device, in casethat an extremely shallow diffusion layer with a depth of not more than10 nm is formed, it is necessary to decrease sufficiently anacceleration voltage in ion implantation. When the acceleration voltageis low, a variation is generated in the distribution of the impurity ina depth direction, so that there is a possibility that the desiredextremely shallow diffusion layer can not be formed. In addition, in thesame manner as in the above-described laser anneal and so on, anapparatus for manufacturing a semiconductor device so as to dope animpurity and an apparatus for manufacturing a semiconductor device so asto anneal a semiconductor substrate are required separately, whichinvites an increase in equipment investment cost.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view schematically showing a main portion inthe order of manufacturing steps of the semiconductor device accordingto a first embodiment;

FIG. 2 is a cross-sectional view schematically showing the main portionin the order of manufacturing steps of the semiconductor deviceaccording to the first embodiment;

FIG. 3 is a cross-sectional view schematically showing the main portionin the order of manufacturing steps of the semiconductor deviceaccording to the first embodiment;

FIG. 4 is a cross-sectional view schematically showing the main portionin the order of manufacturing steps of the semiconductor deviceaccording to the first embodiment;

FIG. 5 is a cross-sectional view schematically showing the main portionin the order of manufacturing steps of the semiconductor deviceaccording to the first embodiment;

FIG. 6 is a cross-sectional view schematically showing the main portionin the order of manufacturing steps of the semiconductor deviceaccording to the first embodiment;

FIG. 7 is a cross-sectional view schematically showing the main portionin the order of manufacturing steps of the semiconductor deviceaccording to the first embodiment;

FIG. 8 is a cross-sectional view schematically showing the main portionin the order of manufacturing steps of the semiconductor deviceaccording to the first embodiment;

FIG. 9 is a cross-sectional view schematically showing the main portionin the order of manufacturing steps of the semiconductor deviceaccording to a first embodiment;

FIG. 10 is a graph schematically showing a change in a temperature of asemiconductor substrate in the main portion of the manufacturing step ofthe semiconductor device according to the first embodiment;

FIG. 11 is a perspective view schematically showing an impurity dopinginto a side wall of a three dimensional structure in the main portion ofmanufacturing step of a semiconductor device according to a secondembodiment;

FIG. 12 is a perspective view schematically showing the structure of thesemiconductor device according to the second embodiment; and

FIG. 13 is a view schematically showing an apparatus for manufacturingthe semiconductor device according to a third embodiment.

DETAILED DESCRIPTION

According to one embodiment, in a method for manufacturing asemiconductor device, a surface region of a semiconductor substrate ismodified into an amorphous layer. A microwave is irradiated to thesemiconductor substrate in which the amorphous layer is formed in adopant-containing gas atmosphere so as to form a diffusion layer in thesemiconductor substrate. The dopant is diffused into the amorphous layerand is activated.

According to another embodiment, in a method for manufacturing asemiconductor device, a surface region of a side wall of a semiconductorlayer is modified into an amorphous layer. The semiconductor layer isformed on a semiconductor substrate. A microwave is irradiated to thesemiconductor layer of which the amorphous layer is formed in the sidewall in a dopant-containing gas atmosphere so as to form a diffusionlayer in the side wall of the semiconductor layer. The dopant isdiffused into the amorphous layer and is activated.

According to further another embodiment, an apparatus for manufacturinga semiconductor device includes a chamber to load a semiconductorsubstrate inside, at least one microwave waveguide connected to thechamber so as to introduce the microwave into the chamber and animpurity gas introducing piping connected to the chamber so as tointroduce the impurity gas into the chamber.

Hereinafter, further embodiments will be described with reference to thedrawings. In the drawings, same reference characters denote the same orsimilar portions.

First Embodiment

A first embodiment will be described with reference to FIGS. 1 to 9.FIGS. 1 to 9 are the cross-sectional views each schematically showing amain portion in the order of manufacturing steps of the semiconductordevice according to the first embodiment.

The embodiment is an example of manufacturing a semiconductor devicewhich includes CMOS (Complementary Metal Oxide Semiconductor)transistors with an extension structure.

To begin with, as shown in FIG. 1, an element isolation region 101 withan STI (Shallow Trench Isolation) structure is formed using a knownmethod on a main surface of a silicon substrate (semiconductorsubstrate) 100 so as to zone a region to form a PMOSFET (hereinafter,referred to simply as “PMOS region”) and a region to form a NMOSFET(hereinafter, referred to simply as “NMOS region”). Next, an N welldiffusion layer 120 is formed in the PMOS region and a P well diffusionlayer 110 is formed in the NMOS region using a well know method. Next,using a known method, in each of the PMOS region and the NMOS region, aninterface layer 131 composed of SiON, a high dielectric constant gateinsulating film 132 composed of HfSiON, a TiN film 133, a gate electrode134 composed of a polycrystalline silicon film doped with impurity, andan offset spacer 135 are formed.

Next, as shown in FIG. 2, an SiO₂ film 140 is deposited on each of theNMOS region and the PMOS region of the silicon substrate 100, and thenthe SiO₂ film 140 of the NMOS region is removed by etching using aresist 141 with an opening portion at the NMOS region formed by a knownmethod as a mask. After that, an upper portion of the silicon substrate100 of the NMOS region is modified into an amorphous portion byimplanting germanium (Ge) ions into the silicon substrate 100 of theNMOS region which is exposed from the SiO₂ film 140. By this, a layer111 which is made amorphous (hereinafter referred to as simply“amorphous layer”) is formed at the upper portion of the siliconsubstrate 100 of the NMOS region. With respect to a method to form theamorphous layer 111, ions of other elements such as argon (Ar), krypton(Kr) and so on may be implanted other than the above-described ionimplantation method by Ge.

By making the upper portion of the silicon substrate 100 amorphous,silicon atoms in the amorphous layer 111 become easy to move. By this,in a process to form an extension diffusion layer described below, itbecomes possible to diffuse and activate dopant effectively in theamorphous layer 111.

In addition, it is preferable that a depth of the amorphous layer 111 isformed deeper than a desired depth of the extension diffusion layerdescribed below. That is, in case that the desired depth of theextension diffusion layer is 10 nm, for example, it is preferable thatthe depth of the amorphous layer 111 is formed deeper than 10 nm. If adepth of the amorphous layer 111 is formed shallower than a depth of theextension diffusion layer, the dopant becomes difficult to be activatedat a region of the extension diffusion layer deeper than the amorphouslayer 111. But, by forming the amorphous layer 111 deeper than thedesired depth of the extension diffusion layer, the dopant is activatedto a depth of the desired depth of the extension diffusion layer, sothat the extension diffusion layer can be effectively formed to thedesired depth. In addition, the term “depth” means a distance from thesurface of the silicon substrate 100 in the direction vertical to thesurface of the silicon substrate 100.

Next, as shown in FIG. 3, after the resist 141 is removed, a microwaveis irradiated to the silicon substrate 100 in the atmosphere of animpurity gas (arsine (AsH₃), or phosphine (PH₃) and so on, for example).By this, the dopant included in the impurity gas diffuses and isactivated in the surface of the silicon substrate 100 of the NMOSregion, so that a diffusion layer (an extension diffusion layer) 112 isformed. A process to form the diffusion layer 112 is performed byintroducing the impurity gas into a chamber (not shown) in which thesilicon substrate 100 is loaded, and in addition introducing a microwaveinto the chamber. In the above-described method to form the diffusionlayer using the microwave, the impurity gas including dopant comes incontact with the silicon substrate 100 in which silicon atoms vibrate orrotate by the irradiation of the microwave, and the dopant diffuses intothe amorphous layer 111 formed in the silicon substrate 100 and inaddition the dopant is activated.

In the vibration or the rotation of the silicon atoms induced in thesilicon substrate by the microwave irradiation, it is possible to keepthe surface temperature of the silicon substrate at a low temperature of200° C. to 600° C. For the reason, while suppressing a rapid diffusionof the impurity due to temperature gradient, a modest diffusion of theimpurity due to Brownian movement takes place, and as the impurity isactivated by the vibration or the rotation of the silicon atoms, anextremely shallow diffusion layer can be formed. In addition, the term“impurity gas” in the embodiment means a gas including dopant to beintroduced into the diffusion layer.

In addition, it is preferable that a frequency of the microwave which isirradiated to the silicon substrate is 2.45 GHz, 5.80 GHz or 24.125 GHzwhich is designated as ISM (Industrial, Scientific and Medical Use)band. That is because a magnetron and so on to generate the microwavecan be obtained at a low price. In addition, the microwave usually usedhas a definite frequency band, and the above-described 2.45 GHz, 5.80GHz or 24.125 GHz is a frequency included in the frequency band of themicrowave to be used.

In addition, a timing to introduce a microwave and an impurity gas intoa chamber will be described with reference to FIG. 10. FIG. 10 is adiagram schematically showing a change in a temperature of a siliconsubstrate caused by irradiating the microwave. As shown in FIG. 10, whenit is started to introduce the microwave in the chamber at t=0 [sec],the temperature reaches a temperature T=T1 [° C.] where the amorphouslayer 111 of the silicon substrate 100 begins to crystallize at t=t1[sec]. When the amorphous layer 111 crystallizes silicon atoms becomedifficult to move, and in the process to form the diffusion layer theamount of the dopant diffusing into the amorphous layer 111 decreases sothat the diffusion layer can not formed effectively. For the reason, itis preferable to start to introduce the impurity gas into the chamberbefore the temperature reaches the temperature (in FIG. 10, T=T1 [° C.])where the amorphous layer 111 begins to crystallize.

In addition, it is preferable that the microwave is introduced into thechamber under the condition that the impurity gas in the chamber is notionized to plasma by the microwave. This is because of preventing thatunnecessary contamination material generates from the wall of thechamber or a jig.

Next, as shown in FIG. 4, the SiO₂ film 140 is removed by etching, andafter an SiO₂ film 142 is deposited on each of the NMOS region and thePMOS region the SiO₂ film 142 of the PMOS region is removed by etchingusing a resist 143 with an opening portion at the PMOS region formed bya known method as a mask. After that, an upper portion of the siliconsubstrate 100 at the PMOS region is modified into an amorphous portionby implanting germanium (Ge) ions into the silicon substrate 100 of thePMOS region which is exposed from the SiO₂ film 142. By this, a layer121 which is made amorphous (hereinafter referred to as simply“amorphous layer”) is formed at the upper portion of the siliconsubstrate 100 of the PMOS region. With respect to a method and conditionand so on to make amorphous is the same as in the case to form theamorphous layer 111 at the NMOS region as described above, and thedescriptions thereof are omitted. Then the resist 143 is removed byetching.

Next, as shown in FIG. 5, after the resist 143 is removed, a microwaveis irradiated to the silicon substrate 100 in the atmosphere of animpurity gas (boron trifluoride (BF₃), or diborane (B₂H₆) and so on, forexample). By this, the dopant included in the impurity gas diffuses inthe surface of the silicon substrate 100 at the PMOS region, so that adiffusion layer (an extension diffusion layer) 122 is formed. A processto form the diffusion layer 122 is performed by introducing the impuritygas into a chamber (not shown) in which the silicon substrate 100 isloaded, and in addition introducing a microwave in the chamber. Withrespect to a condition to irradiate the microwave and an effect causedby using the microwave and so on are the same as in the case to form theamorphous layer 112 as described above, and the descriptions thereof areomitted.

Next, as shown in FIG. 6, after the SiO₂ film 142 is removed by etchinga side wall 113 is formed at the NMOS region by a known method. Then, anN-type source/drain diffusion layer 114 is formed using a resist 144with an opening portion at the NMOS region as a mask. Then, the resist144 is removed by etching.

Next, as shown in FIG. 7, after a side wall 123 is formed at the PMOSregion by a known method, a P-type source/drain diffusion layer 124 isformed using a resist 145 with an opening portion at the PMOS region asa mask. Then, the resist 145 is removed by etching.

Next, as shown in FIG. 8, after an inert gas is introduced into thechamber in which the silicon substrate 100 is loaded, a microwave isintroduced into the chamber. By this, the silicon substrate 100 isannealed in the atmosphere of the inert gas at a temperature of 200° C.to 600° C. by the microwave, and the N-type source/drain diffusion layer114 and the P-type source/drain diffusion layer 124 are activated. Inaddition, as the microwave penetrates through the silicon substrate 100,the microwave can also be used to activate a deep diffusion layer suchas the N-type source/drain diffusion layer 114 and the P-typesource/drain diffusion layer 124.

Next, as shown in FIG. 9, nickel silicide 136 is formed on each of thesurface of the N-type source/drain diffusion layer 114, the surface ofthe P-type source/drain diffusion layer 124, and the upper surfaces ofthe gate electrodes 134, respectively.

As described above, in the embodiment, in case of forming the extensiondiffusion layers (the diffusion layers 112, 122) of the CMOS transistor,a microwave is irradiated to the silicon substrate 100 in the impuritygas atmosphere. By this, it can be made possible to diffuse and activatethe dopant in a low temperature, so that the extremely shallow diffusionlayers can be formed.

In addition, the description was made with respect to the case offorming the extension diffusion layers of the CMOS transistor in theembodiment. But a method for manufacturing a semiconductor deviceaccording to the embodiment is not limited to the case, but can beapplied to cases for forming various extremely shallow diffusion layers.

In addition, the silicon substrate was used as the semiconductorsubstrate in which the diffusion layer is formed in the embodiment. Buta semiconductor substrate in which an extremely shallow diffusion layeris formed is not limited to a silicon substrate, but varioussemiconductor substrates can be used.

Second Embodiment

A method for manufacturing a semiconductor device according a secondembodiment will be described with reference to FIG. 11. FIG. 11 is adiagram showing a main portion of a method for manufacturing asemiconductor device according to a second embodiment, and a schematicdiagram to explain a case that a diffusion layer is formed in a sidewall of a three dimensional structure.

FIG. 11( a) shows typically a case that a diffusion layer is formed in aside wall of a three dimensional structure by a conventional method.Here, a conventional method indicates a method to form a diffusion layerin a semiconductor substrate by an ion implantation and then to activatethe diffusion layer by annealing the semiconductor substrate. FIG. 11(b) shows typically a case that a diffusion layer is formed in a sidewall of a three dimensional structure by a method according to theembodiment. In addition, in the following description with respect tothe embodiment, a direction in parallel with a surface of asemiconductor substrate 200 is referred to as “a horizontal direction”,and a direction perpendicular to the surface of the semiconductorsubstrate 200 is referred to as “a vertical direction”.

As shown in FIG. 11( a), in case that a diffusion layer 202 is formed ina side wall of a semiconductor layer 201 of a three dimensionalstructure by a conventional method, after ions are implanted in the sidewall from an approximately vertical direction (a direction inapproximately parallel with the side wall of the semiconductor layer201), the semiconductor layer 201 is annealed. With respect to an ionimplantation method, there is an oblique ion implantation method, but itis difficult to perform ion implantation in the surface of the side wallof the semiconductor layer 201 from the vertical direction. For thereason, as shown in FIG. 11( a), there is a possibility that thediffusion layer formed by the oblique ion implantation method and so onis not uniform for a depth direction (horizontal direction) of thediffusion layer.

On the other hand, as shown in FIG. 11( b), in case that the diffusionlayer 202 is formed in a side wall of the semiconductor layer 201 of athree dimensional structure by a method according to the embodiment,after an amorphous layer is formed by an ion implantation and so on intothe semiconductor layer 201, a microwave is irradiated to thesemiconductor layer 201 in an impurity gas atmosphere. In the method, itis possible to irradiate the microwave to the surface of the side wallof the semiconductor layer 201 from the approximately verticaldirection. For the reason, as shown in FIG. 11( b), the impurity gascomes in contact with the silicon substrate in which silicon atomsvibrate approximately uniformly by the microwave, and the dopantdiffuses into the amorphous layer formed in the semiconductor layer 201and the dopant is activated, so that an approximately uniform diffusionlayer can be formed. In addition, according to the method, even if theamorphous layer is not formed approximately uniform in the side wall ofthe semiconductor layer 201 for a depth direction, the diffusion layer202 with an approximately uniform depth can be formed by forming theamorphous layer substantially deeper than the depth of the diffusionlayer 202.

Next, with reference to FIG. 12, a case of forming a source/draindiffusion layer of a FinFET will be described to which a method formanufacturing a semiconductor device according to the second embodimentis applied. Processes except a process to form the source/draindiffusion layer of the FinFET are the same as in an existing method, sothat the description is omitted. In addition, the construction of eachportion of the FinFET is the same as an existing construction, so thatthe description is omitted.

FIG. 12 is a perspective view showing the construction of a FinFET. Asshown in FIG. 12, a FinFET includes a gate electrode 215, a gateelectrode side wall 216 and a source/drain region 220 on a semiconductorsubstrate 213 composed of a silicon substrate 210 with a buried oxidefilm 211 formed on the silicon substrate 210.

As shown in FIG. 12, in the construction of the FinFET, the source/drainregion 220 has a three dimensional structure. For the reason, in casethat an impurity diffusion layer is formed in the source/drain region220 of the FinFET, after an amorphous layer is formed in thesource/drain region 220 by an ion implantation and so on, a microwave isirradiated to the source/drain region 220 in an impurity gas atmosphere.By this, the dopant which is included in the impurity gas diffuses inthe surface of the source/drain region 220 and a uniform diffusion layer(the source/drain region 220) can be formed.

As described above, in the embodiment, in case that the diffusion layeris formed in the semiconductor layer of the three dimensional structure,the microwave is irradiated to the semiconductor layer in the impuritygas atmosphere. By this, a diffusion layer which is uniform in thedirection vertical to the surface of the side wall can be formed in theside wall of the semiconductor layer of the three dimensional structure.

Third Embodiment

An apparatus for manufacturing a semiconductor device according to athird embodiment will be described with reference to FIG. 13. FIG. 13 isa pattern diagram showing an apparatus for manufacturing a semiconductordevice which is used for a method for manufacturing a semiconductordevice according to the first embodiment or the second embodiment.

The apparatus for manufacturing a semiconductor device is provided witha chamber 300 to load a silicon substrate inside, microwave waveguides310, 311 each of which is connected to the chamber 300 so as tointroduce a microwave into the chamber 300, and impurity gas introducingpipings 320, 321 each of which is connected to the chamber 300 so as tointroduce an impurity gas into the chamber 300. With respect to themicrowave waveguides 310, 311, without limited to a case that the twoare provided, it may be enough that one or more microwave waveguides areprovided.

A boat 350 is provided in the chamber 300. A silicon substrate 351 isloaded on the boat 350.

Each of the microwave waveguides 310, 311 is connected to a microwaveoutput source such as a magnetron oscillator (not shown) and so on, andintroduces a microwave from the microwave output source into the chamber300. With respect to the microwave output source, a traveling wave tubeoscillator and a klystron oscillator and so on can be supposed exceptthe magnetron oscillator.

Each of the impurity gas introducing pipings 320, 321 introduces animpurity gas into the chamber 300 so as to form a diffusion layer in thesilicon substrate 351 loaded in the chamber 300. The impurity gasintroducing piping 320 is used so as to introduce a gas such as AsH₃,PH₃ and so on into the chamber 300. The impurity gas introducing piping321 is used so as to introduce a gas such as BF₃, B₂H₆ and so on intothe chamber 300.

In addition, an exhaust piping 330 so as to exhaust the gas in thechamber 300 and an inert gas introducing piping 340 so as to introducean inert gas in the chamber 300 are provided to the chamber 300.

In this way, in the apparatus for manufacturing a semiconductor deviceaccording to the embodiment, by providing the microwave wave guides 310,311 and the impurity gas introducing pipings 320, 321, the impurity gascan be introduced in the chamber 300 and in addition the microwave canbe introduced in the chamber 300. By this, it can be made possible toform a desired diffusion layer in the semiconductor substrate loaded inthe chamber 300, as shown in the first embodiment and the secondembodiment.

While certain embodiments have been described, these embodiments havebeen presented by way of example only, and are not intended to limit thescope of the inventions. Indeed, the novel methods and apparatusdescribed herein may be embodied in a variety of other forms;furthermore, various omissions, substitutions and changes in the form ofthe methods and apparatus described herein may be made without departingfrom the spirit of the inventions. The accompanying claims and theirequivalents are intended to cover such forms or modifications as wouldfall within the scope and spirit of the inventions.

1-15. (canceled)
 16. An apparatus for manufacturing a semiconductordevice, comprising: a chamber to load a semiconductor substrate inside;a dopant containing gas introducing piping connected to the chamber soas to introduce a dopant containing gas into the chamber; and at leastone microwave waveguide connected to the chamber so as to introduce themicrowave into the chamber; and under the condition that thedopant-containing gas is not ionized to plasma.
 17. The apparatus formanufacturing the semiconductor device according to claim 16, whereinthe dopant containing gas introducing piping includes both a firstpiping to introduce a p-type dopant- containing gas into the chamber anda second piping to introduce an n-type dopant-containing gas into thechamber.
 18. The apparatus for manufacturing the semiconductor deviceaccording to claim 16, further comprising an inert gas introducingpiping connected to the chamber so as to introduce the inert gas intothe chamber.
 19. The apparatus for manufacturing the semiconductordevice according to claim 16, further comprising an exhaust pipingconnected to the chamber so as to exhaust in the chamber.
 20. Theapparatus for manufacturing the semiconductor device according to claim16, wherein the semiconductor substrate is loaded on a boat provided inthe chamber.
 21. The apparatus for manufacturing the semiconductordevice according to claim 16, wherein the at least one microwavewaveguide is connected to the chamber.
 22. The apparatus formanufacturing the semiconductor device according to claim 16, whereinthe dopant containing gas is introduced into the chamber before anamorphous layer formed on the semiconductor substrate begins tocrystallize.
 23. The apparatus for manufacturing the semiconductordevice according to claim 22, wherein the temperature at which theamorphous layer begins to crystallize is from 200° C. to 600° C.
 24. Theapparatus for manufacturing the semiconductor device according to claim16, wherein the dopant containing gas is either a p-typedopant-containing gas or an n-type dopant-containing gas.)
 25. Theapparatus for manufacturing the semiconductor device according to claim24, wherein the p-type dopant-containing gas is arsine or phosphine 26.The apparatus for manufacturing the semiconductor device according toclaim 24, wherein the n-type dopant-containing gas is arsine orphosphine.